Heretofore it has been known that the apparatus of a digital computer might be arranged in a manner such as to allow accessing to the data storage bits of the computer memory in either of two distinct modes. That is, it has been taught that a system might be developed whereby data can be written into the memory in a word-oriented mode and read from the memory in a bit-oriented mode or vice-versa. That is, data might be written into the memory such that all bits of one word are written simultaneously and one bit of all words are read simultaneously or conversely, one bit of all words are written simultaneously and all bits of one word are read simultaneously. However, "corner-turning" problems have been inherent in prior techniques. These "corner-turning" problems are well understood by those skilled in the art. An oft-used example of such problems is the acquisition, storage, and accessing of radar data. It can be readily understood that if a radar system acquires a plurality of data at various ranges on one azimuth and stores that data in an azimuth-oriented manner and does this for several azimuths it must then devise a unique method to access this stored data if it later desires to access all data at the same range but different azimuths. In other words, if data is acquired and stored in an azimuth-oriented mode and is later to be accessed in a range-oriented mode then unique apparatus or methods must be utilized to make such accessing. In the past, systems have required either complex logic circuitry, redundancy of circuitry or an increased number of memory access lines so as to be above to "turn the corner" from a bit-oriented access to a word-oriented access or vice-versa. Particular approaches toward circumventing the "corner-turning" problem have been numerous. A typical approach to the solution has been shown in U.S. Letter Pat. 3,277,449 for the Orthogonal Computer designed by William Shooman. Certain articles by Mr. Shooman further define and enhance the teachings of this patent. Particularly, chapter 15, entitled "Orthogonal Processing" of the book Parallel Processor Systems, Technologies and Applications edited by L. C. Hobbs and published by Spartan Books in 1970 basically outlines the teachings of the patent. It is readily observable from an understanding of the Shooman Patent that the invention described therein requires both vertical and horizontal accessing means, and vertical and horizontal arithmetical means. In other words, the Shooman invention, and others which have sought to circumvent the "corner-turning" problem, fundamentally teach two separate computers operating upon the same memory. Such systems are extremely expensive due to the requirements of the duplication of access circuitry and arithmetic units.
Further, it has been known that computer systems known as associative processors might be designed whereby arithmetic, search, or other logical operations might be performed upon a plurality of data simultaneously. Such systems have proven themselves to be quite effective in the rapid processing of data. However, heretofore such systems have generally been quite inflexible as to mode of operation; that is, such systems have been capable of simultaneously processing all bits of one word, or one bit of all words, but no given system has been capable of performing simultaneous operations in both modes without the duplication of much of its circuitry such as to use different logic and arithmetic circuitry for each of the two modes.
Therefore, it is the general object of the instant invention to present a novel solid state associative processor organization wherein a unique solid state memory array is coupled with the key apparatus of an associative processor to form an associative array wherein associative or parallel operations may be performed upon data in either a word-oriented or a bit-oriented mode and wherein each mode utilizes the same read-write lines and arithmetic unit.
A further object of the invention is to provide a solid state associative processor organization wherein a plraulity of the aforementioned associative arrays may be operated upon in parallel so as to be capable of simultaneously receiving and processing data from a large number of sources.
A further object of the invention is to provide a control system whereby the control programs necessary for the parallel operation of a plurality of associative arrays may themselves be processed with a speed conducive to that of the associative arrays.
Still a further object of the invention is to provide a unique computer organization which is not only capable of the parallel processing of a large volume of data from various sources and capable of processing the control program with a speed conducive to the data processing speed of the system, but to do so in a manner which is accurate in operation, highly flexible, adaptable to various uses, and quite economical.
The aforesaid objects of the invention and other objects which will become apparent as the description proceeds are achieved by a digital computer wherein operations may be simultaneously performed on a plurality of data in both a bit-oriented mode and a word-oriented mode comprising a plurality of solid state memory arrays, the data storage arrangements of which are such that access may be made to the data storage bits thereof in either a bit-oriented mode or a word-oriented mode, and of such character that a single set of data input/output lines is required for writing data into the arrays or reading data from the arrays in both modes and a plurality of arithmetic units, one associated with each solid state memory array, providing the means for performing, in both word-oriented and bit-oriented modes, parallel logical and arithmetic operations on the data associated with the solid state memory arrays.